1. Field of the Invention
This invention relates to a method for fabricating a field effect transistor, particularly a self-alignment type field effect transistor.
2. Description of the Prior Art
The field effect transistor to be formed by self alignment has hitherto been fabricated by forming a silicon dioxide film having region where the silicon dioxide film becomes thinner at that area on one surface of a silicon semiconductor substrate of a first conductivity type at which the field effect transistor is to be formed, depositing on the silicon dioxide film a polycrystalline silicon layer which has a high impurity concentration, removing the polycrystalline silicon layer by selective etching so as to leave only a part which becomes a gate of the field effect transistor, removing a surface part of the silicon dioxide film over the entire area by employing as a mask the part of the polycrystalline silicon layer to become the gate and, to the extent that the surface of the silicon semiconductor substrate is exposed at the other part in the region, forming a source and a drain by doping substrate surface portions thus exposed with an impurity of a second conductivity type opposite to the first conductivity type of the semiconductor substrate, forming a silicon dioxide film on the entire area which includes a surface of the polycrystalline silicon layer to become the gate and the exposed surface of said semiconductor substrate, forming windows for source, drain and gate electrodes in the silicon dioxide film, depositing a metallic conductor over the entire area, and forming said metallic conductor into a predetermined pattern by selective etching so as to obtain the source, drain and gate electrodes. According to such a method, in order to prevent the source and drain electrodes from overlying the polycrystalline silicon layer serving as the gate, in the selective etching step of forming connection holes for the electrodes, the interval between each of the connection holes for the source and drain electrodes and the polycrystalline silicon layer serving as the gate is selected, at the present technical level, to be at least 3.mu.m in consideration of the magnitude of the side etching of the connection hole and the reproducbility of the mask registration. For this reason, the prior art has had the disadvantage that a high density of integration cannot be attained.